A 3.5 GHz self-aligned single-clocked binary frequency divider on GaAs

A fully planar self-aligned technology has been ultilised to fabricate a monolithic single-clocked binary frequency divider consisting of a gated master/slave flip-flop and a complementary clock-pulse generator to drive it. An optimised version of the gated m.s. flip-flop is presented along with the m. e.s.f.e.t.model used for the simulations. Correct counting from d.c. up to 5.5 GHz for the gated m.s. flip-flop and up to 3.5 GHz for the single-clocked divider are reported. The performance and evaluation of the circuits are dealt with in detail.