DocumentCode
3558264
Title
Modelling of small MOS devices and device limits
Author
Chatterjee, Pallab K. ; Yang, Ping ; Shichijo, Hisashi
Author_Institution
Texas Instruments Inc., Dallas, USA
Volume
130
Issue
3
fYear
1983
fDate
6/1/1983 12:00:00 AM
Firstpage
105
Lastpage
126
Abstract
The paper reviews the various approaches to the modelling of small-geometry MOS devices. The physics and interaction of device properties in small MOSFETs are discussed as they apply to device and circuit design for VLSI. It is shown that statistical fluctuation of device geometry and the effect of parasitics is the primary determinant of circuit performance. Scaling theory for MOSFETs and limits to scaling are examined in the context of geometry and high-field effects. It is concluded that the incentives to scale geometries below 0.5 ¿m are small.
Keywords
field effect integrated circuits; insulated gate field effect transistors; large scale integration; reviews; semiconductor device models; MOSFET; VLSI; circuit design; device geometry; device limits; effect of parasitics; high-field effects; modelling; review; scaling theory; small-geometry MOS devices;
fLanguage
English
Journal_Title
Solid-State and Electron Devices, IEE Proceedings I
Publisher
iet
Conference_Location
6/1/1983 12:00:00 AM
ISSN
0143-7100
Type
jour
DOI
10.1049/ip-i-1.1983.0023
Filename
4642692
Link To Document