Transit and storage times of bipolar transistors in a VLSI environment

The main objective of the work is to study the effects of the physical and technology parameters on the delay times of bipolar transistors in a VLSI environment. Expressions for the transit time in a very narrow base, and the storage time due to the minority charge in the emitter region will be derived. The analysis will be performed using typical substrate (which is the emitter in I2 L structures having zero epitaxial width) profiles, obtained from measurements. The results and conclusions can be used to tailor an optimum impurity profile that gives minimum storage time.