The boundary scan

Miniaturization trends in integrated circuit (IC) technology have caused many testing problems. As bigger packaged ICs with higher pin counts are more densely packed onto a printed circuit board (PCB), accessing an IC´s pins is harder. No longer are the pins mechanically accessible to probes or a bed-of-nails fixture. Therefore, determining which IC or interconnect is faulty is difficult or impossible. Because each IC´s input pins cannot be controlled, and each IC´s output pins cannot be observed. The boundary scan method was developed with the goal of improving this controllability and observability problem. A shift-register is included next to each IC pin so that input and output values can be serially shifted in and out. This reduces the need to use probes to control and observe. Also, the output of each IC´s scan register can be connected with the input of another IC´s scan register. This effectively creates one big scan chain per PCB, further reducing points that must be mechanically probed. The inclusion of a scan-register on each IC allows: 1) the observation of each IC during normal operation; 2) the test of interconnects between ICs, and 3) the isolation of the IC from others so it can test itself. The IEEE Standard 1149.1 Test Access-Port and Boundary Scan defines the test logic for implementing a boundary scan test architecture. Example circuits were designed in CMOS. A boundary scan cell is described