• DocumentCode
    3558699
  • Title

    Verification of Pin-Accurate Port Connections

  • Author

    Lee, Geeng-Wei ; Huang, Juinn-Dar ; Wang, Chun-Yao ; Jou, Jing-Yang

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    25
  • Issue
    5
  • fYear
    2008
  • Firstpage
    478
  • Lastpage
    486
  • Abstract
    Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.
  • Keywords
    formal verification; program diagnostics; system-on-chip; IP blocks; SoC; pin accurate interfaces; pin accurate port connections verification; port connection verification flow; Computer errors; Electronic design automation and methodology; Fault detection; Hardware design languages; LAN interconnection; Multichip modules; Pattern analysis; Probes; Testing; Wiring;
  • fLanguage
    English
  • Journal_Title
    Design Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2008.149
  • Filename
    4648429
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3558699