DocumentCode :
3559118
Title :
An Implicit Approach to Minimizing Range-Equivalent Circuits
Author :
Chen, Yung-Chih ; Wang, Chun-Yao
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
Volume :
27
Issue :
11
fYear :
2008
Firstpage :
1942
Lastpage :
1955
Abstract :
Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous approaches use the binary decision diagram (BDD) technique to compute the range of one circuit and then reconstruct the circuit using the computed range. Although the size of the new circuit is significantly reduced due to the range rearrangement, this method suffers from the BDD blowup problems for large circuits since performing range computation using BDD is memory intensive. Thus, in this paper, we propose a new method for simplifying combinational circuits without explicit range computation. We first introduce a new concept of a stuck-at fault test for a circuit´s range, showing that a range untestable stuck-at fault on a primary input (PI) indicates that this PI is range redundant, i.e., it can be removed without affecting the circuit´s range. We then present a procedure to determine if a given range stuck-at fault on a PI is untestable. Our method iteratively identifies and removes range-redundant PIs to simplify a combinational circuit without performing range computation. Accordingly, large circuits that BDD-based methods cannot deal with can be handled using our method. We conduct experiments on a set of ISCAS´85 and MCNC benchmarks, and the experimental results show that our approach can minimize circuits such that fewer PIs are left. On average, our approach gets 37.06% reduction in terms of the number of PIs and 36.31% reduction in terms of the node counts.
Keywords :
benchmark testing; binary decision diagrams; combinational circuits; fault diagnosis; logic testing; ISCAS´85 benchmark; MCNC benchmark; binary decision diagram technique; combinational circuit; combinational equivalence checking; random simulation; range-equivalent circuits; range-preserving simplification; range-redundant primary input; stuck-at fault test; Binary decision diagrams; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Data structures; Helium; Logic; Range-preserving simplification; range-redundant primary input (PI);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.2006088
Filename :
4655567
Link To Document :
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