• DocumentCode
    3559294
  • Title

    Defect Tolerance for Nanoscale Crossbar-Based Devices

  • Author

    Tehranipoor, Mohammad ; Rad, Reza M P

  • Author_Institution
    Univ. of Connecticut, Storrs, CT
  • Volume
    25
  • Issue
    6
  • fYear
    2008
  • Firstpage
    549
  • Lastpage
    559
  • Abstract
    The need for defect maps and per-chip placement and routing limits the efficiency of test and defect tolerance techniques in nanoscale crossbar-based devices. The authors propose a method using two simulation programs that circumvents these difficulties to find fault-free implementations of logic functions on defective crossbars.
  • Keywords
    circuit simulation; fault diagnosis; integrated circuit testing; logic circuits; nanoelectronics; defect maps; defect tolerance; logic functions; nanoscale crossbar-based devices; per-chip placement; routing limits; simulation programs; test efficiency; CMOS technology; Circuit faults; Fault tolerance; Logic devices; Logic functions; Logic testing; Nanobioscience; Nanoscale devices; Programmable logic arrays; Redundancy;
  • fLanguage
    English
  • Journal_Title
    Design Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2008.162
  • Filename
    4702879
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3559294