Title :
A Systematic Approach to Memory Test Time Reduction
Author :
Yeh, Jen-Chieh ; Chen, Chao-Hsun ; Wu, Cheng-Wen ; Kuo, Shuo-Fen
Abstract :
This article describes a method for reducing overall memory test time without sacrificing fault coverage. Key to this method is a test time reduction tool that helps remove redundant test items from the test flow, merge existing test patterns, and develop efficient new test patterns.
Keywords :
integrated circuit testing; semiconductor storage; fault coverage; memory test time reduction; redundant test items; systematic approach; test flow; test patterns; Algorithm design and analysis; Automatic testing; Costs; Pattern analysis; Probes; Random access memory; Semiconductor device testing; Semiconductor memory; Statistical analysis; System testing;
Journal_Title :
Design Test of Computers, IEEE
DOI :
10.1109/MDT.2008.152
