The Effect of Negative $V_{\rm TH}$ of nand Flash Memory Cells on Data Retention Characteristics

We present our study on the dependence of data retention characteristics on the threshold voltage (V _TH) of the cell transistor revealing the combined effect of control gate voltage and cell transistor architecture. Data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim (FN) stress mainly occurs in tunnel oxide away from the region where maximum cell on-current flows. In the sub-50-nm region, due to short distance between the control gate and the shallow-trench isolation (STI) corner, the maximum cell on-current position is shifted from the STI corner to the channel center as control gate voltage decreases. The edge-thin tunnel oxide cell transistor, of which cell on-current flow is separated from tunneling current in negative cell V _TH, shows 0.12-V superior data retention characteristic than the edge-thick tunnel oxide cell transistor at -3 V of cell transistor V _TH in experiment.