Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations

In this paper, a low latency angle recoding method for the higher bit-width parallel coordinate rotation digital computer (CORDIC) rotator implementations is proposed. In previous studies, parallel CORDIC (para-CORDIC) rotators have been used to reduce the computational bottleneck by precomputing the required rotation directions. However, the number of required microrotations increases with the bit-width of the input angle, leading to extra stages compared to the conventional CORDIC. To overcome this, our proposed method can obtain a reduced number of microrotations for larger bit-width implementations by recoding two bits of the input angle in the first few area-consuming stages concurrently. This leads to above 21% area/delay reduction compared to previously reported 64-bit para-CORDIC methods. We have implemented our proposed 64-bit para-CORDIC rotator implementations using 0.13- mum CMOS technology, and the operating speed can achieve 250 MHz.