A CMOS Image Sensor With In-Pixel ADC, Timestamp, and Sparse Readout

Recent developments in CMOS image sensors have focused on the advancement of digital pixel sensors (DPS). A novel DPS aiming to combine multiple functionalities on the imaging plane has been designed and tested: The on pixel intelligent CMOS (OPIC) sensor was manufactured in a 0.25 mum logic process with 5 metal layers, and 8 mum epitaxial layers. The sensor comprises three 2 x 2 mm test arrays of 30 mum pixels. Two of the test arrays are named "advanced" and include two 8-bit DRAM cells, one 8-bit ROM cell, and one 1-bit DRAM cell per pixel. The 8-bit DRAM cells can record both ADC and "time-to-threshold" data, while the ROM hard codes the pixel address within the array. The 1-bit DRAM acts as a "hit flag" enabling automatic sparsification of the image data based on an external threshold. Results of the device simulation, design and electro-optical testing are presented. The OPIC sensor is shown to have ~50 e-read noise, 105 ke- full well capacity, 10% fill factor, and a measured power consumption of 230 mW when operated at 1000 fps. A 79% reduction in frame size is achieved when imaging a point-like object in sparse mode. Capacitive coupling from digital signal lines was observed in certain modes of operation of the sensor. An alternative coding scheme was devised to quantify this and the effect was found to be most evident at ADC units of less than 2.5 mV. A number of applications are proposed for the functionality available on OPIC. The test structure is demonstrated in a high-speed tracking application and shown to have a 100 ns resolution. This device holds promise for tracking applications where a high position and time accuracy is required.