Addressing Cu/Low- $k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies

Low-k dielectrics, which are beneficial for chip resistance-capacitance (RC) delay improvement, crosstalk-noise minimization, and power-dissipation reduction, are indispensable for the continuous scaling of advanced VLSI circuits, particularly that of high-performance logic circuits. In this paper, several critical challenges for Cu/low-k time-dependent dielectric-breakdown (TDDB)-reliability qualification will be reviewed. First, a low-k TDDB field-acceleration model and its determination will be discussed. Second, the macroscopic interconnect line-to-line spacing variation across the wafer and the microscopic line-to-line spacing nonuniformity induced by line-edge roughness within the same test structure and their impacts on low- k TDDB reliability will be carefully examined. The Weibull shape-parameter dependence on applied stress voltage due to such global and local spacing variations will be analyzed. Finally, the moisture effect on low-k TDDB and capacitance stability as an example of the impact from process integration will be reported, demonstrating that low-k TDDB is sensitive to back-end-of-the-line integration.