Title :
Analysis of the logic model used in selective precharge
Author :
Wang, Shao-Yi ; Zukowski, Charles A.
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Abstract :
Selective precharge is a technique that has been derived for reducing the energy used in large fan-in logic arrays. The limits of the simplistic logic model used in earlier work on selective precharge are carefully studied here. The accuracy of this model under different probability distributions of connections in an array and the potential impacts of input signal bias and correlations among input signals are discussed
Keywords :
logic arrays; low-power electronics; fan-in; logic array; logic model; low-power design; probability distribution; selective precharge; CMOS logic circuits; Capacitance; Logic arrays; Logic circuits; Logic gates; Performance analysis; Semiconductor device modeling; Statistics; Voltage;
Conference_Titel :
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location :
Las Cruces, NM
Print_ISBN :
0-7803-5491-5
DOI :
10.1109/MWSCAS.1999.867216
