A 0.8-μm CMOS, 622 Mb/s SDH/SONET communication system

Author

de Vasconcelos, Eduardo ; Aguiar, Rui L. ; Santos, Daniel M.

Author_Institution

Dept. de Electron. e Telecoms, Aveiro Univ., Portugal

Volume

1

fYear

1999

fDate

1999

Firstpage

232

Abstract

This paper describes a 0.8 μm CMOS communication system designed for 622 Mb/s SDH/SONET links. The single-chip system implements all line interface functions needed by the link. The emitter performs parallel bus interface, parallel-to-serial conversion and optional scrambling for line testing. An output buffer to attack the laser driver is also included. The receiver performs post-amplification, clock recovery, frame detection and optional descrambling, followed by serial-to-parallel conversion and parallel bus interface

Keywords

CMOS digital integrated circuits; SONET; synchronous digital hierarchy; 0.8 micron; 622 Mbit/s; CMOS single-chip system; SDH/SONET link; clock recovery; descrambling; emitter; frame detection; high-speed digital communication; laser driver; line testing; optical fiber; output buffer; parallel bus interface; parallel-to-serial conversion; post-amplification; receiver; scrambling; serial-to-parallel conversion; Circuits; Clocks; Delay; Flip-flops; Multiplexing; Polynomials; SONET; Synchronous digital hierarchy; Topology; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867250

Filename

867250