Architecture for a smart Reed-Solomon decoder

This paper describes a VLSI architecture for a Smart Reed-Solomon Decoder (SRSD). The SRSD use the RS code both as an forward error correction code and as an error control code. It uses information about the reliability of the received symbols to select “a priori” one (or more) efficient decodings that combine correction of errors and erasures. Once the decoding is processed, the SRSD also performs an “a posteriori” evaluation of the decoding process in order to reject low reliability decoded codewords