Monolithic phase-locked loop circuits with coarse-steering acquisition aid

This paper describes a dual-loop PLL circuit that provides for wide range acquisition. A dual-loop architecture, consisting of a regular PLL circuit and a coarse-steering circuit is presented. The coarse-steering circuit assists the regular PLL to operate in a correct active frequency range, while the regular loop converges on the final frequency and phase. The entire circuit is designed for implementation in MOSIS 1.2 μm CMOS technology. HSPICE simulation shows the PLL can obtain lock-in over a frequency range of 160-440 MHz with a 3-volt power supply