Design and PLD implementation of a group demultiplexer

Author

Ho, H. ; Szwarc, V. ; Loo, C. ; Kwaniewski, T.

Author_Institution

Commun. Res. Centre Canada, Ottawa, Ont., Canada

Volume

1

fYear

1999

fDate

1999

Firstpage

504

Abstract

This paper presents the design and PLD implementation of a multi carrier group demultiplexer for 8, 16, and 32 channels based on the Polyphase-FFT architecture. The circuit implementations she based on Altera´s EPF10K250 SRAM PLD devices. Circuit simulation results presented confirm that the group demultiplexer circuits, operating over a fixed frequency bandwidth and configured for 8, 16, and 32 channels support the intended signal data rates of T1, T1/2, and T1/4 respectively. The group demultiplexer implementations presented here are intended to form the building blocks of a reconfigurable unit capable of supporting different data rates

Keywords

SRAM chips; demultiplexing equipment; fast Fourier transforms; programmable logic devices; Altera EPF10K250; Polyphase-FFT architecture; SRAM PLD device; circuit simulation; design; multi-carrier group demultiplexer; reconfigurable unit; Bandwidth; Circuit simulation; Demodulation; Demultiplexing; Filter bank; Finite impulse response filter; Frequency; Satellites; Signal design; Source separation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867315

Filename

867315