DocumentCode
3561104
Title
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 
s Frequency Acquisition Time
Author
Jung, Inhwa ; Shin, Daejung ; Kim, Taejin ; Kim, Chulwoo
Author_Institution
Dept. of Electron. & Electr. Eng., Korea Univ., Seoul, South Korea
Volume
19
Issue
7
fYear
2011
fDate
7/1/2011 12:00:00 AM
Firstpage
1310
Lastpage
1315
Abstract
This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The RMS jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.
Keywords
CMOS integrated circuits; jitter; phase detectors; phase locked loops; radio transceivers; radiofrequency integrated circuits; 1P5M CMOS technology; RMS jitter; bit rate 140 Mbit/s to 1.96 Gbit/s; dead-zone problem; external reference clock; frequency 70 MHz; frequency acquisition time; linear phase detector; low-jitter performance; multiband PLL; phase adjustment; power 388 mW; referenceless transceiver; self-initialization technique; size 0.25 mum; time 11.4 ns; time 7.2 mus; voltage 2.5 V; wide-range transceiver design; CMOS technology; Clocks; Detectors; Frequency; Jitter; Low voltage; Phase detection; Phase locked loops; Transceivers; Transmitters; Clock and data recovery (CDR); embedded clock; linear PD; low voltage differential signaling (LVDS); low-jitter; transceiver; wide-range;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
Conference_Location
6/7/2010 12:00:00 AM
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2010.2047953
Filename
5482002
Link To Document