An efficient test vector compression technique based on geometric shapes [system-on-a-chip]

One of the prime challenges of testing a system-on-a-chip (SOC) is to reduce the required test data size. In this paper, we introduce a novel geometric shapes based compression/decompression scheme that substantially reduces the amount of test data and hence reduces test time. The proposed scheme is based on reordering the test vectors in such a way that it enables the generation of geometric shapes that can be highly compressed via perfect lossless compression. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the proposed technique in achieving very high compression ratio. Compared to published results, our technique achieves significantly higher compression ratio