DocumentCode
356237
Title
CMOS implementation and performance of β-bit serial/parallel multipliers
Author
Wei, Jian ; Qian, Xiaoming ; Siferd, Raymond
Author_Institution
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Volume
2
fYear
1999
fDate
1999
Firstpage
613
Abstract
This paper presents unique hardware implementations for 3 β-bit serial/parallel multipliers with 16-bit operands. The circuits were fabricated with a 1.2 μm CMOS process and compared for circuit area, power dissipation, speed, throughput, and latency. The results illustrate the flexibility of the serial/parallel architecture in satisfying a wide range of signal processing requirements
Keywords
CMOS logic circuits; digital arithmetic; high-speed integrated circuits; multiplying circuits; β-bit serial/parallel multipliers; 1.2 micron; 16 bit; CMOS implementation; circuit area; hardware implementations; latency; operation speed; performance comparison; power dissipation; serial/parallel architecture; signal processing requirements; throughput; Arithmetic; Circuit testing; Clocks; Delay; Hardware; Parallel architectures; Power dissipation; Product design; Signal processing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location
Las Cruces, NM
Print_ISBN
0-7803-5491-5
Type
conf
DOI
10.1109/MWSCAS.1999.867713
Filename
867713
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