An ultra-low power consumption and very compact 1.49 GHz CMOS Voltage Controlled Ring Oscillator

Author

Duc Xuan Tran ; Trinh Trong Dang

Author_Institution

Centre of Technol., RMIT Vietnam Univ., Ho Chi Minh City, Vietnam

fYear

2014

Firstpage

239

Lastpage

244

Abstract

In this paper, a three-stage Voltage Controlled Ring Oscillator, designed and implemented using IBM 130nm CMOS technology with Cadence Virtuoso tools, is presented. The initial specification for the output frequency is 400MHz-1GHz, but our proposed design could generate the oscillation range from 82.72KHz to 1.49GHz when control voltage is from 0.0V to 1.2V. Furthermore, the power consumption is extremely low 30.5 uW at 1GHz and the layout is very compact with an active area of 42.3um². Besides that, the phase noise is -101.33 dB/Hz at 1MHz offset from 1.37 MHz center frequency. Comparisons with existing VCO designs show a big improvement of our design in terms of power consumption and area.

Keywords

CMOS analogue integrated circuits; UHF oscillators; low-power electronics; phase noise; voltage-controlled oscillators; CMOS voltage controlled ring oscillator; Cadence Virtuoso tools; IBM CMOS technology; frequency 82.72 kHz to 1.49 GHz; phase noise; power 30.5 muW; power consumption; size 130 nm; three-stage voltage controlled ring oscillator; ultralow power consumption; voltage 0 V to 1.2 V; Frequency control; Inverters; Layout; Transistors; Voltage control; Voltage-controlled oscillators; CMOS; VCO; compact layout; low power; phase noise; ring oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Technologies for Communications (ATC), 2014 International Conference on

Print_ISBN

978-1-4799-6955-5

Type

conf

DOI

10.1109/ATC.2014.7043391

Filename

7043391