RTL implementation for a specific ALU of the 32-bit VLIW DSP processor core

Author

Khoi-Nguyen Le-Huu ; Anh-Vu Dinh-Duc ; Quoc-Minh Dang-Do ; Trong-Tu Bui

Author_Institution

Univ. of Inf. Technol., Ho Chi Minh City, Vietnam

fYear

2014

Firstpage

387

Lastpage

392

Abstract

Digital Signal Processors (DSPs) have shown the great strengths in digital signal processing algorithms such as digital filtering and Fourier analysis. This work is about an implementation for a specific computational unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is described from top-level to gate-level design and then it is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board.

Keywords

digital signal processing chips; fixed point arithmetic; instruction sets; reduced instruction set computing; Fourier analysis; RISC ISA; RISC instruction set architecture; RTL implementation; VLIW fixed-point DSP processor core; altera cyclone II FPGA board; data computational unit; digital filtering; digital signal processing algorithms; digital signal processors; gate-level design; modelsim software; specific ALU; top-level design; word length 32 bit; Assembly; Clocks; Computer architecture; Digital signal processing; Hardware; Registers; VLIW; ALU; Digital Signal Processors; RISC; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Technologies for Communications (ATC), 2014 International Conference on

Print_ISBN

978-1-4799-6955-5

Type

conf

DOI

10.1109/ATC.2014.7043417

Filename

7043417