TTA as predictable architecture for real-time applications

Timing requirements of an embedded system are usually met by real-time scheduling techniques. However, realtime scheduling cannot provide guarantees without the knowledge of worst case execution time (WCET). Modern dynamically scheduled microprocessors improve their average case performance by incorporating complex features such as pipelines, caches, branch prediction, out-of-order and speculative execution. However, these features make WCET analysis difficult and complicated. Furthermore, worst case execution time itself is compromised for better average case execution times. In this paper, we propose Transport Triggered Architectures (TTA) as time-predictable hardware architectures for real-time systems. TTAs consist of Function Units (FU), Register Files (RF) and the main memory connected using an interconnection network. The compiler is responsible to schedule instructions containing data transports between FUs and/or RFs. In TTA, static scheduling makes predicting WCET easier. Exposed datapath with static control at data transport level and wide range of choice of FUs impart performance comparable to a dynamically scheduled microprocessor. Thus making it ideal for use in applications with timing constraints. Experimental results are provided to show competitive performance and timing predictability provided by TTA.