Design and implementation of efficient reversible even parity checker and generator

Author

Gayathri, S.S. ; Ananthalakshmi, A.V.

Author_Institution

Dept. of ECE, Inst. of Res. Technol., Siruvachur, India

fYear

2014

Firstpage

1

Lastpage

4

Abstract

Communication in today´s world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.

Keywords

data communication; digital communication; logic gates; 3-bit reversible even parity checker; Feynman gate; Modelsim; Peres gate; Toffoli gate; Xilinx Virtex5vlx30tff665-3; digital communication; digital data transmission; error free transmission; generator circuit; parity generator; reversible gates; Generators; Integrated circuit modeling; Logic circuits; Logic gates; Power dissipation; Receivers; Simulation; Feynman gate; New gate; Parity checker and generator; Peres gate; Reversible logic; Toffoli gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Science Engineering and Management Research (ICSEMR), 2014 International Conference on

Print_ISBN

978-1-4799-7614-0

Type

conf

DOI

10.1109/ICSEMR.2014.7043605

Filename

7043605