Designing of Area and Power Efficient Modulo 2N Multiplier

Modulo multiplication forms the basic block of Residue Number System (RNS) based Digital signal processing and cryptographic applications. Several techniques are proposed to concise the computation complexity of the multiplier design. In this paper the area and power efficient modulo 2^N multiplier for {2^N-1, 2^N, 2^N+1} based RNS is designed involving Logarithmic Number System (LNS) concept. The divided approximation based error correction circuits for logarithmic and antilogarithmic converters are designed to improve the accuracy of the conversion process. The power and area consumption values of the proposed work are compared with modulo multiplier designed using Radix-8 booth encoding technique. From the simulation results it has been found that the area occupied and power consumed by this work are about 56.76% and 60.25% lesser compared with the existing technique. This paper involves in the multiplier design with the number of bits, N= 8, 16 and 32 using Advanced Design System (ADS) tool with 0.35 μm CMOS technology.