• DocumentCode
    3563969
  • Title

    Low-power comparator design based on CMOS dynamic logic circuit

  • Author

    Patel, Chandrahash ; Veena, C.S.

  • Author_Institution
    Technocrats Inst. of Technol., Bhopal, India
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Here a new design of comparator is proposed which is based half precharged CMOS dynamic logic just by introducing few more transistors as précharge, transmission transistor which not only reduces the leakage current but improves the power consumption of circuit. For simulation, designing Microwind & DSCH software with 120/70 nm technology is used.
  • Keywords
    CMOS logic circuits; comparators (circuits); integrated circuit design; low-power electronics; DSCH software; Microwind software; half precharged CMOS dynamic logic circuit; leakage current reduction; low-power comparator design; power consumption improvement; size 120 nm; size 70 nm; transmission transistor; CMOS integrated circuits; CMOS technology; Delays; Integrated circuit modeling; Layout; Logic circuits; Transistors; Delay; Dynamic Logic; Half precharged; Power optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), 2014 2nd International Conference on
  • Print_ISBN
    978-1-4799-6985-2
  • Type

    conf

  • DOI
    10.1109/ET2ECN.2014.7044932
  • Filename
    7044932
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3563969