Title :
An energy saving cache algorithm
Author_Institution :
SITE, Vellore Inst. of Technol., Vellore, India
Abstract :
Traditional caches have fixed number of sets. This paper proposes cache architecture with variable number of cache sets. The cache is assumed to be of fixed size. The cache operates assuming one set. On conflict, the number of sets is doubled selectively enabling the cache sets. An algorithm for address mapping is defined. The sets that are unoccupied are put in off mode. The occupied sets operate in high power mode. The proposed model is simulated with SPEC2K benchmark. An energy saving of 10% is observed with improvement in average memory access time by 76% compared with set associative cache of same size.
Keywords :
cache storage; memory architecture; power aware computing; SPEC2K benchmark; address mapping; average memory access time; cache architecture; cache sets; energy saving cache algorithm; Benchmark testing; Computational modeling; Computer architecture; Computers; Energy consumption; Mathematical model; Program processors; average memory access time; energy saving; set associative cache; variable set architecture;
Conference_Titel :
Computational Science and Technology (ICCST), 2014 International Conference on
DOI :
10.1109/ICCST.2014.7045191