A modular hardware platform for brain-computer interface

The contribution presents a novel high-performance, low power BCI architecture allowing a single-chip implementation of a BCI device. FPGA platform is used to reach high performance and low power consumption; to speed up the development cycle, high-level synthesis of DSP algorithms is employed. A novel highly modular architecture with many advantages (configurability, possibility of independent development, topological compatibility with 2D FPGA fabric, scalability, and high computational power) is proposed. The first block of the system is designed to prove the feasibility of the whole concept. Usage of high level synthesis is shown to reduce the development time about ten times compared to the standard RTL flow while generating design small enough so as we may fit the complete BCI pipeline into one FPGA device.