A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs

The optimal design of successive approximation register (SAR) analog-to-digital converters (ADCs) requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge-redistribution digital-to-analog converters (DACs). Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a novel MATLAB-based numerical tool to assist the design of classic, split and with attenuation capacitor binary weighted capacitive array topologies with an even number of bits from 6 to 14. The tool allows to perform both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances in order to compute both differential- (DNL) and integral nonlinearity (INL). Signal-to-noise plus distortion ratio (SNDR) and Effective Number of Bits (ENoB) degradation due to static non-linear effects is also estimated. An excellent agreement with the results obtained by the available circuit simulators (e.g. Cadence Spectre) is shown but featuring up to 10^4-times shorter simulation time.