Title :
A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
Author :
Natarajan, S. ; Agostinelli, M. ; Akbar, S. ; Bost, M. ; Bowonder, A. ; Chikarmane, V. ; Chouksey, S. ; Dasgupta, A. ; Fischer, K. ; Fu, Q. ; Ghani, T. ; Giles, M. ; Govindaraju, S. ; Grover, R. ; Han, W. ; Hanken, D. ; Haralson, E. ; Haran, M. ; Hecksche
Author_Institution :
DTS, Intel Corp., Hillsboro, OR, USA
Abstract :
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.
Keywords :
MOSFET; SRAM chips; integrated circuit interconnections; semiconductor doping; silicon; 2nd-generation FinFET transistor; 4th generation high-k metal gate; 6th-generation strained silicon; SRAM cell; Si; air-gapped interconnects; critical patterning layer; logic technology; performance-critical layer; rectangular fins; self-aligned double patterning; size 0.0588 mum; size 14 nm; size 42 nm; size 8 nm; subfin doping technique; Doping; FinFETs; Logic gates; Market research; Random access memory;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7046976
