Data cache architecture of the superscalar by scheduling patterns

A novel data cache architecture for the out-of-order issue superscalar processor architecture is presented. The superscalar method is based on the scheduling patterns that describe predetermined out-of-order execution for four instructions stored in a programmable logic array. To exploit instruction-level parallelism, the authors propose an effective memory address conflict avoidance scheme for the data cache. The approach is to resolve alias resolution by hardware to maintain object code compatibility and also augment instruction-level parallelism. The performance of the proposed architecture on selected benchmark programs was simulated