Title :
First experimental demonstration of Ge CMOS circuits
Author :
Heng Wu ; Conrad, Nathan ; Wei Luo ; Ye, Peide D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We report the first experimental demonstration of Ge CMOS circuits, based on a novel recessed channel and S/D technique. Aggressively scaled non-Si CMOS logic devices with channel lengths (Lch) from 500 to 20 nm, channel thicknesses (Tch) of 25 and 15 nm, EOTs of 4.5 and 3 nm and a small width ratio (Wn:Wp=1.2) are realized on a Ge-on-insulator (GeOI) substrate. The CMOS inverters have high voltage gain of up to 36 V/V, which is the best value among all of the non-Si CMOS results by the standard top-down approach. Scalability studies on Ge CMOS inverters down to 20 nm are carried out for the first time. NAND and NOR logic gates are also investigated.
Keywords :
CMOS logic circuits; germanium; invertors; logic gates; CMOS circuits; CMOS inverters; CMOS logic devices; Ge; Ge-on-insulator substrate; NAND; NOR; logic gates; size 15 nm; size 25 nm; size 3 nm; size 4.5 nm; size 500 nm to 20 nm; Aluminum oxide; CMOS integrated circuits; Inverters; Iterative closest point algorithm; Logic gates; Nickel; Noise;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047016
