First experimental demonstration of Ge CMOS circuits

We report the first experimental demonstration of Ge CMOS circuits, based on a novel recessed channel and S/D technique. Aggressively scaled non-Si CMOS logic devices with channel lengths (L_ch) from 500 to 20 nm, channel thicknesses (T_ch) of 25 and 15 nm, EOTs of 4.5 and 3 nm and a small width ratio (W_n:W_p=1.2) are realized on a Ge-on-insulator (GeOI) substrate. The CMOS inverters have high voltage gain of up to 36 V/V, which is the best value among all of the non-Si CMOS results by the standard top-down approach. Scalability studies on Ge CMOS inverters down to 20 nm are carried out for the first time. NAND and NOR logic gates are also investigated.