DocumentCode :
3565135
Title :
First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications
Author :
Hashemi, Pouya ; Balakrishnan, Karthik ; Engelmann, Sebastian U. ; Ott, John A. ; Khakifirooz, Ali ; Baraskar, Ashish ; Hopstaken, Marinus ; Newbury, Joseph S. ; Chan, Kevin K. ; Leobandung, Effendi ; Mo, Renee T. ; Dae-Gyu Park
Author_Institution :
IBM Res., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2014
Abstract :
For the first time, we report fabrication and characterization of high-performance s-Si1-xGex-OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrate realization of s-SiGe fins with WFIN =3.3nm and devices with LG=16nm, in a CMOS compatible process. Using a Si-cap-free passivation, we report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1013cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. We also report the highest performance reported to date among sub-20nm-LG pMOS FinFETs at VDD=0.5V. In addition, hole transport as well as electrostatics, performance and leakage characteristics of SGOI FinFETs for various dimensions are comprehensively studied in this work.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; elemental semiconductors; germanium; insulators; passivation; CMOS compatible process; Ge-Si1-0.5Ge0.5; Si-cap-free passivation; aggressively scaled fin dimension; distance 16 nm; electrostatics; high hole mobility; high-content strained-insulator; size 25 nm; size 3.3 nm; subLG pMOS FinFET; voltage 0.5 V; Electrostatics; FinFETs; Logic gates; Passivation; Silicon; Silicon germanium; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
Type :
conf
DOI :
10.1109/IEDM.2014.7047061
Filename :
7047061
Link To Document :
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