Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

Author

Nguyen, P. ; Barraud, S. ; Tabone, C. ; Gaben, L. ; Casse, M. ; Glowacki, F. ; Hartmann, J.-M. ; Samson, M.-P. ; Maffini-Alvaro, V. ; Vizioz, C. ; Bernier, N. ; Guedj, C. ; Mounet, C. ; Rozeau, O. ; Toffoli, A. ; Alain, F. ; Delprat, D. ; Nguyen, B.-Y. ;

Author_Institution

LETI, CEA, Grenoble, France

fYear

2014

Abstract

We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NWs (gate length L_G=15 nm) with +90% I_ON current improvement.

Keywords

CMOS integrated circuits; Ge-Si alloys; elemental semiconductors; field effect transistors; hole mobility; nanowires; semiconductor materials; silicon; NFET; PFET; Si; Si-channel n-FET; SiGe; cSiGe; dual-channel CMOS co-integration; hole mobility enhancement; hybrid channel Ω-gate CMOS nanowires; nanowire device architecture; strained SiGe-channel p-FET; ultra-scaled p-FET NW; CMOS integrated circuits; Degradation; Logic gates; Silicon; Silicon germanium; Strain; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2014 IEEE International

Type

conf

DOI

10.1109/IEDM.2014.7047062

Filename

7047062