Author :
Mitard, J. ; Witters, L. ; Arimura, H. ; Sasaki, Y. ; Milenin, A.P. ; Loo, R. ; Hikavyy, A. ; Eneman, G. ; Lagrain, P. ; Mertens, H. ; Sioncke, S. ; Vrancken, C. ; Bender, H. ; Barla, K. ; Horiguchi, N. ; Mocuta, A. ; Collaert, N. ; Thean, A.V.-Y.
Abstract :
This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a GM,SAT,EXT / SSSAT of 250 μS.μm-1 / 130 mV.dec-1 (at the targeted VDS=0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.
Keywords :
Ge-Si alloys; MOSFET; nickel alloys; phosphorus; semiconductor device testing; semiconductor doping; CMOS-compatible processing steps; NiSiGe; P; RMG; STI formation; WFIN inversion-mode n-FinFET; contact scheme; in-situ phosphorus-doped raised-source-drain; junctionless n-FET; relaxed-Germanium n-FinFET; replacement metal gate; size 15 nm; voltage 0.5 V; Implants; Junctions; Logic gates; Metals; Passivation; Silicon; Transistors;
