Mismatch in high-K metal gate process analog design

This paper presents mismatch behaviors of high-K metal gate transistors when used in analog design applications. The data collected shows the sensitivity of mismatch in the high-K metal gate process to the overall layout environment, including top-metal routing placement, which was not reported before this work. We compared data from different fabrication sources, which indicated that mismatch can be improved through process as well as through layout strategy.