Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Author

Wei, A. ; Singh, J. ; Bouche, G. ; Zaleski, M. ; Augur, R. ; Senapati, B. ; Stephens, J. ; Lin, I. ; Rashed, M. ; Yuan, L. ; Kye, J. ; Woo, Y. ; Zeng, J. ; Levinson, H. ; Wehbi, A. ; Hang, P. ; Ton-That, V. ; Kanagala, V. ; Yu, D. ; Blackwell, D. ; Beece,

Author_Institution

GLOBAL FOUNDRIES, Malta, NY, USA

fYear

2014

Abstract

Continuous process-level and system-level innovation has driven Moore´s Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

Keywords

MOSFET; analogue integrated circuits; elemental semiconductors; high-k dielectric thin films; low-k dielectric thin films; semiconductor device manufacture; semiconductor device packaging; silicon; system-on-chip; FinFET; I/O scaling; Moore law scaling; Si; SoC technology; analog scaling; continuous process level; cost scaling; high-k device; low-k device; low-resistance materials; multidie package integration; patterning materials; semiconductor manufacturing; size 10 nm; strained Si device; system-level innovation; FinFETs; Layout; Random access memory; Standards; System-on-chip; Technological innovation; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2014 IEEE International

Type

conf

DOI

10.1109/IEDM.2014.7047076

Filename

7047076