A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials

Erase saturation issue is a fundamental challenge for SONOS-type charge-trapping NAND Flash devices. Nowadays the most popular way to solve this issue is to pursue either curvature-induced field enhancement effect in the nano-wire SONOS device, or HK/MG to suppress the gate injection. However, both approaches have its drawback and reliability challenges. In this work, we propose a completely different approach that utilizes a double-trapping (or double storage) layer in a barrier engineered (BE) SONOS device to overcome the erase saturation ideally. A second nitride trapping layer (N3) is stacked on top of the first blocking oxide (O3) and 1st trapping layer (N2) of the original BE-SONOS device. Both theoretical model and experimental measured results indicate that when N3 stores sufficient electron charge it can greatly suppress gate injection, allowing continuous hole injection into N2 that gives a very deep erased Vt ~ -6V. A fully-integrated 3D Vertical Gate (VG) NAND Flash test chip using this novel device has been fabricated which demonstrates excellent MLC operation window and reliability. The flat and planar topology of this double-trapping BE-SONOS device enables minimal design rule of 3D NAND Flash array and possesses superb read disturb immunity.