Study of the piezoresistive properties of NMOS and PMOS Ω-gate SOI nanowire transistors: Scalability effects and high stress level

Author

Pelloux-Prayer, J. ; Casse, M. ; Barraud, S. ; Nguyen, P. ; Koyama, M. ; Niquet, Y.-M. ; Triozon, F. ; Duchemin, I. ; Abisset, A. ; Idrissi-Eloudrhiri, A. ; Martinie, S. ; Rouviere, J.-L. ; Iwai, H. ; Reimbold, G.

Author_Institution

Leti, CEA, Grenoble, France

fYear

2014

Abstract

We hereby present a comprehensive study of piezoresistive properties of aggressively scaled MOSFET devices. For the first time, the evolution of the piezoresistive coefficients with scaled dimensions is presented (gate length down to 20nm and channel width down to 8nm), and from the low to high stress regime (above 1GPa). We have shown that the downscaling of geometrical parameters doesn´t allow the use of the conventional definition of piezoresistivity tensor elements. The obtained results give a comprehensive insight on strain engineering ability in aggressively scaled CMOS technology.

Keywords

MOSFET; nanowires; piezoresistance; silicon-on-insulator; Ω-gate SOI nanowire transistors; CMOS technology; NMOS; PMOS; aggressively scaled MOSFET devices; geometrical parameter downscaling; high stress regime; piezoresistive properties; piezoresistivity tensor elements; scalability effects; strain engineering ability; MOS devices; Piezoresistance; Silicon; Silicon germanium; Strain; Stress; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2014 IEEE International

Type

conf

DOI

10.1109/IEDM.2014.7047090

Filename

7047090