Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

We demonstrate monolithic 3D integration of logic and memory in arbitrary vertical stacking order with the ability to use conventional inter-layer vias to connect between any layers of the 3D IC. We experimentally show 4 vertically-stacked layers (logic layer followed by two memory layers followed by another logic layer), enabled by the integration of traditional silicon-FETs (on the bottom-most layer) with low-processing-temperature emerging nanotechnologies: metal-oxide resistive random-access memory (RRAM), and carbon nanotube-FETs (CNFETs). As a demonstration, we show a routing element of a switchbox for a field-programmable gate array (FPGA), with each component of the routing element (involving both logic and memory elements) on their own vertical layer.