BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities

Author

Groeseneken, G. ; Franco, J. ; Cho, M. ; Kaczer, B. ; Toledano-Luque, M. ; Roussel, Ph ; Kauerauf, T. ; Alian, A. ; Mitard, J. ; Arimura, H. ; Lin, D. ; Waldron, N. ; Sioncke, S. ; Witters, L. ; Mertens, H. ; Ragnarsson, L.-A. ; Heyns, M. ; Collaert, N. ;

Author_Institution

Dept. of Electr. Eng. (ESAT), KU Leuven, Leuven, Belgium

fYear

2014

Abstract

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

Keywords

Ge-Si alloys; MOSFET; elemental semiconductors; nanoelectronics; negative bias temperature instability; semiconductor device reliability; silicon; BTI reliability; NBTI; SiGe; beyond-silicon devices; carrier-defect decoupling; silicon-based pMOS devices; stochastic behavior; sub 1-nanometer EOT MOSFET devices; time dependent variability; Benchmark testing; Hafnium compounds; Logic gates; MOSFET; Reliability; Silicon; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2014 IEEE International

Type

conf

DOI

10.1109/IEDM.2014.7047168

Filename

7047168