Title :
An efficient low-power binding algorithm in high-level synthesis
Author :
Choi, Yoonseo ; Kim, Taewhan
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
6/24/1905 12:00:00 AM
Abstract :
We propose an efficient binding algorithm for power optimization in high-level synthesis. In prior work, it has been shown that several binding problems for low-power can be formulated as multi-commodity flow problems (due to an iterative execution of data flow graph) and be solved optimally. However, since the multi-commodity flow problem is NP-hard, the application is limited to a class of small sized problems. To overcome the limitation, we address the problem of how we can effectively make use of the property of efficient flow computations in a network so that it is extensively applicable to practical designs while producing close-to-optimal results. To this end, we propose an efficient two-step algorithm, which (1) determines a feasible binding solution by partially utilizing the computation steps for finding a maximum flow of minimum cost in a network and then (2) refines it iteratively. Experiments with a set of benchmark examples show that the proposed algorithm saves the run time significantly while maintaining close-to-optimal bindings in most practical designs.
Keywords :
circuit optimisation; computational complexity; data flow graphs; high level synthesis; NP-hard; benchmark examples; close-to-optimal bindings; data flow graph; feasible binding solution; flow computations; high-level synthesis; low-power binding algorithm; multi-commodity flow problems; power optimization; two-step algorithm; Computer networks; Computer science; Cost function; High level synthesis; Portable computers; Power dissipation; Processor scheduling; Registers; Scheduling algorithm; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010455