• DocumentCode
    3565829
  • Title

    Overview of Fan-out Wafer Level Package (FO-WLP)

  • Author

    Lu, Charlie

  • Author_Institution
    Altera Corp., San Jose, CA, USA
  • fYear
    2014
  • Firstpage
    208
  • Lastpage
    208
  • Abstract
    Summary form only given. IC packaging technology has been evolving fast and diversely in the past decade, from high-end to low-end application, such as 3D IC integration with TSV, 2.5D with TSV-Si interposer, Package-on-Package (PoP), Fan-Out Wafer-Level-Package (FO-WLP), and so on. Among the various technologies, FO-WLP get significant attention with its high-degree heterogeneous integration capability, small form factor, and total reduced system cost. FO-WLPs cover wide range of applications, e.g., FPGA, GPU, networking, smartphone / tablet Application Processor (AP), Base Band (BB) module, RF / WiFi module, Power Amplifier (PA) module, etc. There are two categories of FO-WLP, one is characterized with molding encapsulant plus wafer-like process; the other one is characterized with PCB-like (or substrate-like) process. In order to distinguish the two categories, the later one is called Panel FO-WLP, while the former one is still called FO-WLP. According to the nature of wafer-like processed FO-WLP, it possesses fine-line-fine-space, typically 1um ~ 5um, and small via capability, which implies the package could accommodate more I/Os, better electrical performance, and thus high-end to mid-range application. Nevertheless Panel FO-WLP uses substrate-like process, it cannot provide too fine-line trace, typically the line width is wider than 10um, but with lower cost. Thus, its application is limited to mid-range to low-end devices. For FO-WLP, several companies have its own intellectual proprietary (IP), such as Infineon´s eWLB (embedded Wafer Level Ball Grid Array), Freescale´s RCP (Redistributed Chip Package), and TSMC´s InFO WLP (Integrated Fan-Out WLP). For Panel FO-WLP, the same, each company has its own IP: such as Imbera´s 1MB (Integrated Module Board), AT&S´s ECP (Embedded Components Packaging), ASE´s a-EASI (advanced - Embedded Assembly Solution Integration), and J-Devices´ WFOP (Wide Strip Panel Fan-out Package). This paper will review and compa- e the major players´ package construction, their process uniqueness, and discuss the potential extension and application of the FO-WLPs.
  • Keywords
    encapsulation; industrial property; moulding; printed circuits; three-dimensional integrated circuits; wafer level packaging; 3D IC integration; ASE a-EASI; AT&S ECP; Freescale RCP; IC packaging technology; IP; Imbera 1MB; Infineon eWLB; J-Devices WFOP; PCB-like process; PoP; TSMC InFO WLP; TSV-Si interposer; advanced-embedded assembly solution integration; embedded components packaging; embedded wafer level ball grid array; fan-out wafer level package; fine-line trace; fine-line-fine-space; high-degree heterogeneous integration capability; integrated fan-out WLP; integrated module board; intellectual proprietary; molding encapsulant plus wafer-like process; package-on-package; panel FO-WLP; redistributed chip package; small form factor; substrate-like process; total reduced system cost; wafer-like processed FO-WLP; wide strip panel fan-out package; Decision support systems; IEEE catalog;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014 9th International
  • Type

    conf

  • DOI
    10.1109/IMPACT.2014.7048396
  • Filename
    7048396