DocumentCode :
3565862
Title :
Printing method for redistribution layer and filling of through silicon vias using sintering silver paste
Author :
Chia-Yen Lee ; Hsin-Chang Tsai
Author_Institution :
Delta Electron., Inc., Taoyuan, Taiwan
fYear :
2014
Firstpage :
466
Lastpage :
469
Abstract :
The increasing requirement for higher performance and reduced form factor has driven advanced packaging solutions such as chip stacking assembly. Through Silicon Vias (TSVs) can offer speed and power reduction while offering the possibility of advanced wafer-level 3D packaging or stacking of various types of micro-components directly on a CMOS chip. Redistribution layer (RDL) is a key enabling technology for 3D integration through the release of design constraints on the pitch and diameters of interconnects. In addition, these methods enable some of the packaging steps to be carried out at the wafer level, which offers many advantages in terms of throughput and economies of scale over traditional single die packaging techniques. This article reports the results obtained by screen printing using low-temperature sintered silver paste to successfully fill TSVs or RDL which are two important technologies for wafer level packaging. In this article we present an alternative process flow, which aims to replace steps such as seed layers deposition by physical vapor deposition (PVD) and Cu plating to fill the vias with a screen and stencil printing step followed by the curing of the printed medium. This process could also potentially allow the redistribution layer to be printed at the same time as the vias filling stage. It is important to develop materials with better electrical, thermal and thermomechanical properties that can be processed at low temperature to interconnect future semiconductor devices. Silver paste with micrometer-size particles is commonly used in microelectronic packages due to the high electrical and thermal performance of silver. However, high sintering temperatures (>600°C) make them impractical for semiconductor device interconnection. This paper will use low-temperature sintered silver paste as a new device interconnection material, and the effects of printing parameters, material and stencil design were all analyzed in this investigat- on. Using appropriate printing parameters can obtain better integrity and roughness of pattern and different curing curves of low-temperature sintered silver (Ag) paste will cause tremendous difference of shrinkage rate. This paper has demonstrated that a novel low-temperature sintered silver paste is capable of printing down to 100μm diameter of TSVs using a conventional screen printer. Such a conventional screen printing TSVs has advantages over traditional physical vapor deposition or metal plating including the cost effective and easy to manufacture. The redistribution layer as small as 100μm were successfully printed using through hole apertures located on the same screen used for printing the TSVs thereby making it a dual purpose stencil / screen hybrid.
Keywords :
CMOS integrated circuits; copper; filling; integrated circuit interconnections; printing; silver; sintering; three-dimensional integrated circuits; vapour deposition; wafer level packaging; Ag; CMOS chip; Cu; chip stacking assembly; copper plating; filling method; packaging solutions; physical vapor deposition; printing method; redistribution layer; screen printing; seed layers deposition; semiconductor device interconnection; sintering silver paste; stencil printing; through silicon via; wafer level 3D packaging; wafer level packaging; IEEE catalog;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014 9th International
Type :
conf
DOI :
10.1109/IMPACT.2014.7048410
Filename :
7048410
Link To Document :
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