High speed SerDes design verification

Serial data (SerDes) link has been widely used in gigabit rate link, storage applications, telecom, data communications, etc. The ability to accurately predict SerDdes channel insertion loss and return loss plays a critical role in prediction of SerDes link performance. Two test vehicles are designed to demonstrate the step-by-step modeling technique. One is the bare package sample, and the other is the package on print circuit board (PCB) sample. In this paper, the SerDes signals are designed on both test vehicles and characterized through model to measurement correlation in section I. Section II shows the step-by-step modeling procedure to correlate SerDes model with measurement on bare package sample and the step-by-step modeling technique is validated up to 19 GHz. In section III, the details of measurement technique are discussed in order to guarantee the accuracy of measured data. In section IV, we present the SerDes design reference for operating at 5 GHz and 12.5 GHz depend on the differential insertion loss and near-end coupling performance of bare package and package on PCB in this study. Final are conclusions.