An effective and efficient approach for layer assignment with thermal through-silicon-vias planning

Three-dimensional integrated circuit (3D IC) process technology can improve the circuit speed and reduce the power dissipation. However, because of low thermal conductivities of dielectrics between active layers, the heat generated by the stacked layers results in a large temperature increase, which may degrade the circuit speed and reduce the circuit reliability. Previous work uses integer linear programming, which is an NP-hard approach, at the high-level design stage to deal with the simultaneous layer assignment and thermal TSVs planning for reducing the temperature increase. In this paper, we propose a heuristic algorithm to perform layer assignment with thermal TSVs planning in polynomial time complexity. Experimental results show that our approach is effective and efficient for reducing the temperature increase.