Title :
Comparing FICDM and wafer-level CDM test methods: Apples to Oranges?
Author :
Jack, Nathan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
The on-chip stresses induced by FICDM, WCDM2, CC-TLP, and VF-TLP are compared on the basis of voltage monitor readings and IC functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics increase the FICDM current rise-time at an I/O pad relative to that measured externally, causing miscorrelation with wafer-level testers.
Keywords :
failure analysis; integrated circuit reliability; integrated circuit testing; wafer level packaging; CC-TLP; FICDM; I/O pad; IC functional failures; VF-TLP; WCDM2; capacitively- coupled TLP; core circuit failures; field-induced charge device model; on-chip stresses; package-related parasitics; voltage monitor readings; wafer level packaging; wafer-level CDM; wafer-level CDM test methods; wafer-level testers; Current measurement; Electrostatic discharges; Logic gates; Receivers; Stress; Stress measurement; Voltage measurement;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Print_ISBN :
978-1-4673-1467-1
