BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

We present a review of our recent studies of BTI in FET devices fabricated in different material systems, highlighting the reliability opportunities and challenges of each device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies when a Si cap is used to passivate the channel and to fabricate a standard SiCh/HfCh gate stack. We ascribe this superior reliability to a reduced interaction of channel holes with oxide defects, thanks to a favorable energy alignment of the (Si)Ge Fermi level to the dielectric stack We discuss gate stack optimization (Ge fraction, quantum well and Si cap thicknesses, channel strain engineering) for maximum BTI reliability, and we propose a simple model able to reproduce all the experimental trends. We then invoke the model to understand the excessive BTI in other high-mobility channel gate stacks, as Ge/GeOx/high-k and InGaAs/high-k Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability.