Modeling of hot carrier injection across technology scaling

Hot carrier Injection mechanism is an important reliability concern of CMOS devices. While the critical gate dimension length is scaled down, this mechanism of degradation is exacerbated due to the increase of the local electrical field. For different planar and FinFET of N-channel MOS technology nodes, the scalability of this mechanism is presented and discussed. The underlying physical mechanism involved in HCI condition is reviewed and discussed. Stress renormalization through age rate function for several technology nodes is presented. At circuit level, predictive simulation can be handled with Design-for-Reliability framework. Interactions between degradation mechanisms involved in HCI are accounted in the simulation.