Reliability of fully-integrated nanoscale ReRAM/CMOS combinations as a function of on-wafer current control

Resistive random access memory (ReRAM) is a novel form of non-volatile memory expected to replace FLASH memory in the near future. As a further step toward use of ReRAM in computer architectures, we have developed a CMOS/ReRAM hybrid process, integrating ReRAM into a CMOS process flow. In this study, we investigate yield, reliability, endurance, threshold voltages (forming, set and reset voltages) of ReRAM devices implemented in the back end of the line (BEOL). The focus of this study is on single ReRAM devices operated with an external transistor (1T1R configuration). Yield and endurance of these 1T1R configured devices show a strong dependence on device position on the wafer, the device size, and the current compliance used during the initial forming and subsequent set sweeps. Elevated temperatures resulted in a shift of the optimum operation conditions and could be used to improve device performance. Variance in performance of the ReRAM devices was directly correlated with manufacturing issues and material properties to gain maximum information for future improvements.